Interlaced Partition Multiplier

Interlaced Partition Multiplier

A new apparatus for fast multiplication of two numbers is introduced. Inputs are split into partitions, and one number is replaced by two with zeros interlaced in every other partition. Products are computed with no carries between partitions, in the time required to multiply the short partitions an...

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Veröffentlicht in:IEEE transactions on computers 2016-08, Vol.65 (8), p.2672-2677
Hauptverfasser: Fritz, Christopher, Fam, Adly T.
Format: Artikel
Sprache:eng
Schlagworte:
Adders
Algorithms
Arrays
CMOS
CMOS integrated circuits
Complexity theory
Computer simulation
cost/performance
Delays
high-speed arithmetic
Integrated circuits
Mathematical models
Multiplication
multiplier
Multipliers
Partitions
Very large scale integration
VLSI
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Beschreibung
Zusammenfassung:A new apparatus for fast multiplication of two numbers is introduced. Inputs are split into partitions, and one number is replaced by two with zeros interlaced in every other partition. Products are computed with no carries between partitions, in the time required to multiply the short partitions and add the partial sums. Component adders and multipliers can be chosen to trade off area and speed. A new graphical tool is used to compare this multiplier to existing ones based on CMOS VLSI simulations.
ISSN:0018-9340
1557-9956
DOI:10.1109/TC.2015.2481379