Basic analysis of false turn-on phenomenon of power semiconductor devices with parasitic inductances
False turn-on phenomenon is a critical problem in power converters. The key factor in the analysis of the phenomenon is the Cdv/dt. However, this factor is not so important any longer if parasitic inductances are taken into account. The mathematical analysis reported presents that the false turn-on...
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| Veröffentlicht in: | Electronics letters 2016-06, Vol.52 (13), p.1158-1160 |
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| creator | Umegami, H Ishibashi, H Nanamori, K Hattori, F Yamamoto, M |
| description | False turn-on phenomenon is a critical problem in power converters. The key factor in the analysis of the phenomenon is the Cdv/dt. However, this factor is not so important any longer if parasitic inductances are taken into account. The mathematical analysis reported presents that the false turn-on problem with parasitic inductances is characterised by two frequencies and four types of balancing factors. The peak gate oscillation voltage can also be evaluated in two different cases. These peak values are evaluated by comparing the mathematical results with simulation results by PSIM and the errors are 5.60 and 2.99%. |
| doi_str_mv | 10.1049/el.2016.1057 |
| format | Article |
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The key factor in the analysis of the phenomenon is the Cdv/dt. However, this factor is not so important any longer if parasitic inductances are taken into account. The mathematical analysis reported presents that the false turn-on problem with parasitic inductances is characterised by two frequencies and four types of balancing factors. The peak gate oscillation voltage can also be evaluated in two different cases. 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The key factor in the analysis of the phenomenon is the Cdv/dt. However, this factor is not so important any longer if parasitic inductances are taken into account. The mathematical analysis reported presents that the false turn-on problem with parasitic inductances is characterised by two frequencies and four types of balancing factors. The peak gate oscillation voltage can also be evaluated in two different cases. These peak values are evaluated by comparing the mathematical results with simulation results by PSIM and the errors are 5.60 and 2.99%.</description><subject>Computer simulation</subject><subject>Electric potential</subject><subject>Electronics</subject><subject>false turn‐on phenomenon</subject><subject>Gates</subject><subject>Mathematical analysis</subject><subject>parasitic inductances</subject><subject>peak gate oscillation voltage</subject><subject>Power converters</subject><subject>Power electronics, energy conversion and sustainability</subject><subject>Power semiconductor devices</subject><subject>PSIM</subject><subject>Voltage</subject><issn>0013-5194</issn><issn>1350-911X</issn><issn>1350-911X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2016</creationdate><recordtype>article</recordtype><recordid>eNp9kE9r2zAYh8VoYSHtbR9Ahx16mFO9-mf7uIZkLRh2WWE3IcuvqYZjeZLTkG8_pRmsh7UH8SJ-D88r_Qj5BGwFTNa3OKw4A50vqvxAFiAUK2qAnxdkwRiIQkEtP5LrlHzLQILUTMKCdHc2eUftaIdj8omGnvZ2SEjnfRyLMNLpCcewy2c8ZVM4YKQJd96Fsdu7OUTa4bN3mOjBz090sjEL56z0L7kdc3RFLl-k13_nkjxuNz_W90Xz_dvD-mtTOFFqUVS8khVXuudSVcxxixK6vnQ1dq3qJLS6LplWgkGFrOXcMacdh77Fqsy5FUtyc_ZOMfzeY5rNzieHw2BHDPtkINuV1qKUGf1yRl0MKUXszRT9zsajAWZOfRoczKlPc-oz4-qMH_yAx3dZs2kafrdlopbi34s8zuZXyJ3m_7-14vN_0E3zyjx1vfgDcPWRsA</recordid><startdate>20160623</startdate><enddate>20160623</enddate><creator>Umegami, H</creator><creator>Ishibashi, H</creator><creator>Nanamori, K</creator><creator>Hattori, F</creator><creator>Yamamoto, M</creator><general>The Institution of Engineering and Technology</general><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>F28</scope><scope>FR3</scope><scope>L7M</scope></search><sort><creationdate>20160623</creationdate><title>Basic analysis of false turn-on phenomenon of power semiconductor devices with parasitic inductances</title><author>Umegami, H ; Ishibashi, H ; Nanamori, K ; Hattori, F ; Yamamoto, M</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c3763-82848256f24580c2ae41df7c9edb5d41b6970653018e0b22c0c6c21fbe875d4a3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2016</creationdate><topic>Computer simulation</topic><topic>Electric potential</topic><topic>Electronics</topic><topic>false turn‐on phenomenon</topic><topic>Gates</topic><topic>Mathematical analysis</topic><topic>parasitic inductances</topic><topic>peak gate oscillation voltage</topic><topic>Power converters</topic><topic>Power electronics, energy conversion and sustainability</topic><topic>Power semiconductor devices</topic><topic>PSIM</topic><topic>Voltage</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Umegami, H</creatorcontrib><creatorcontrib>Ishibashi, H</creatorcontrib><creatorcontrib>Nanamori, K</creatorcontrib><creatorcontrib>Hattori, F</creatorcontrib><creatorcontrib>Yamamoto, M</creatorcontrib><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>Electronics letters</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Umegami, H</au><au>Ishibashi, H</au><au>Nanamori, K</au><au>Hattori, F</au><au>Yamamoto, M</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Basic analysis of false turn-on phenomenon of power semiconductor devices with parasitic inductances</atitle><jtitle>Electronics letters</jtitle><date>2016-06-23</date><risdate>2016</risdate><volume>52</volume><issue>13</issue><spage>1158</spage><epage>1160</epage><pages>1158-1160</pages><issn>0013-5194</issn><issn>1350-911X</issn><eissn>1350-911X</eissn><abstract>False turn-on phenomenon is a critical problem in power converters. The key factor in the analysis of the phenomenon is the Cdv/dt. However, this factor is not so important any longer if parasitic inductances are taken into account. The mathematical analysis reported presents that the false turn-on problem with parasitic inductances is characterised by two frequencies and four types of balancing factors. The peak gate oscillation voltage can also be evaluated in two different cases. These peak values are evaluated by comparing the mathematical results with simulation results by PSIM and the errors are 5.60 and 2.99%.</abstract><pub>The Institution of Engineering and Technology</pub><doi>10.1049/el.2016.1057</doi><tpages>3</tpages></addata></record> |
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| subjects | Computer simulation Electric potential Electronics false turn‐on phenomenon Gates Mathematical analysis parasitic inductances peak gate oscillation voltage Power converters Power electronics, energy conversion and sustainability Power semiconductor devices PSIM Voltage |
| title | Basic analysis of false turn-on phenomenon of power semiconductor devices with parasitic inductances |
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