Basic analysis of false turn-on phenomenon of power semiconductor devices with parasitic inductances

False turn-on phenomenon is a critical problem in power converters. The key factor in the analysis of the phenomenon is the Cdv/dt. However, this factor is not so important any longer if parasitic inductances are taken into account. The mathematical analysis reported presents that the false turn-on problem with parasitic inductances is characterised by two frequencies and four types of balancing factors. The peak gate oscillation voltage can also be evaluated in two different cases. These peak values are evaluated by comparing the mathematical results with simulation results by PSIM and the errors are 5.60 and 2.99%.