Carrier-less fault-tolerant stochastic synthesis in multi-cell multi-level converters: a central limit approach to highly-dimensional power electronic systems

As the number of cells in multi-level converters increase, issues related to the high number of subsystems enter the power electronics area. Within this frame, this study presents a carrier-less approach to the voltage synthesis across the series of several voltage-source cells in multi-level converter topologies. The key idea is the exploitation of a stochastic-based choice of the discrete cell output voltage, operating according to a local, independent random variable. When the number of cells is sufficiently high, the law of large numbers and the central limit theorem (CLT) of the probability theory guarantee that the synthesis of the total voltage lies in a known interval with high probability. Because of the CLT stochastic properties, an increased number of cells inherently leads to more robust and fault-tolerant waveforms, also due to the reduced capacitors required in each cell. The absence of deterministic modulation reduces the hardware cost (cabling and control) and requires no reconfiguration in case of cell failures. This work focuses on the theoretical and hardware-in-the-loop validation of the main principle, including an analysis of the capacitance requirements for each cell. The method could be also applied to current-source multi-level converters based on parallel connections of current-source cells.