Efficient bridgeless PFC converter with reduced voltage stress

Summary An efficient bridgeless power factor correction converter with reduced voltage stress is proposed. In the proposed converter, the input full‐bridge rectifier is removed to reduce the conduction loss of rectification, and the voltage stress of switching devices is significantly reduced by utilizing the additional circuit composed of a capacitor and a diode. Therefore, low‐voltage‐rating diodes with less forward voltage drop and low‐voltage‐rating Metal‐Oxide‐Semiconductor Field‐Effect Transistor (MOSFET) with low RDS(on) is utilized. The proposed converter is based on the single‐ended primary‐inductor converter power factor correction operation in discontinuous conduction mode to achieve a high power factor with a simple control circuit. Consequently, the proposed converter can provide a high power factor and a high power efficiency, and it is also suitable for low‐cost converter for high input/output voltage system. The operational principles, steady‐state analysis, and design equations of the proposed converter are described in detail. Experimental results are verified for a 130 W prototype at a constant switching frequency 100 kHz. Copyright © 2015 John Wiley & Sons, Ltd. Efficient bridgeless power factor correction converter with reduced voltage stress is proposed. In the proposed converter, the input full‐bridge rectifier is removed and voltage stresses of switching devices are reduced. Because of the absence of the input bridge diode and utilization of switching devices of low voltage rating, conduction losses are significantly reduced and high efficiency is achieved.