Experimental Evaluation of Circuit-Based Modeling of the NBTI Effects in Double-Gate FinFETs

In this work, an example of practical implementation of the auxiliary sub-circuit (ASC) for modeling of the NBTI effects in DG FinFETs is described. A good agreement between the simulated and measured electrical characteristics of p-type DG FinFETs fabricated in SOI technology has been obtained using the industry-standard BSIM-CMG model with ASC. The oxide and interface trap densities are extracted in Spice simulations by tuning the ASC trapped charge parameters to fit the NBTI experimental data. The increase of oxide and interface trapped charge in p-type DG FinFET device is found to follow the logarithmic dependence with NBTI stress time.