Fast and accurate architectural vulnerability analysis for embedded processors using Instruction Vulnerability Factor

Scaling new-silicons to nano-scale era has brought more integration, high performance and low power consumption while the reliability becomes a serious challenge for integrated circuits technology. Therefore, reliability awareness has become essential in early stages of integrated circuit design. Since many of modern chips scrimmage with the limited power budget and traditional techniques such as N-Modular Redundancy (NMR) is not efficient for non-uniform fault tolerance, accurate analyzing of the reliability of different hardware components or application parts is necessary. Transient and soft errors which are resulted from cosmic rays strike and Process Voltage and Temperature (PVT) variation are known as main sources of unreliability. Recently, Architectural Vulnerability Factor (AVF) is widely used for analyzing the reliability of a processors. In this paper, we have introduced a new metric named as Instruction Vulnerability Factor (IVF) which is used for fast, accurate, and recurring AVF estimation. Special scenarios have been developed which enable us to utilize exhaustive fault injection for precise IVF calculation for a given processor instruction set. IVFs of a special instruction considers the vulnerability of pipeline stages while executing the instruction. Finally, a simple equation has been derived for AVF estimation based on running instructions. Our experimental results which are extracted by our Configurable Reliability Analysis Framework (CRAF) confirm the accuracy of presented AVF estimation method. Moreover, IVF can be employed by reliability aware compilation or online AVF estimation techniques.