Solution-processed carbon nanotube thin-film complementary static random access memory

Thin-film transistors made from solution-processed single-walled carbon nanotubes are used to fabricate large-scale integrated arrays of complementary static random access memory cells. Over the past two decades, extensive research on single-walled carbon nanotubes (SWCNTs) has elucidated their many extraordinary properties 1 , 2 , 3 , making them one of the most promising candidates for solution-processable, high-performance integrated circuits 4 , 5 . In particular, advances in the enrichment of high-purity semiconducting SWCNTs 6 , 7 , 8 have enabled recent circuit demonstrations including synchronous digital logic 9 , flexible electronics 10 , 11 , 12 , 13 , 14 and high-frequency applications 15 . However, due to the stringent requirements of the transistors used in complementary metal–oxide–semiconductor (CMOS) logic as well as the absence of sufficiently stable and spatially homogeneous SWCNT thin-film transistors 16 , 17 , 18 , the development of large-scale SWCNT CMOS integrated circuits has been limited in both complexity and functionality 19 , 20 , 21 . Here, we demonstrate the stable and uniform electronic performance of complementary p-type and n-type SWCNT thin-film transistors by controlling adsorbed atmospheric dopants and incorporating robust encapsulation layers. Based on these complementary SWCNT thin-film transistors, we simulate, design and fabricate arrays of low-power static random access memory circuits, achieving large-scale integration for the first time based on solution-processed semiconductors.