Tutorial T10: Post - Silicon Validation, Debug and Diagnosis

Summary form only given, as follows. The complete presentation was not made available for publication as part of the conference proceedings. Drastic increase in design complexity along with the emergence of new failure mechanisms in the nanometer regime has led to significant increase in the complexity of verification, validation, and debug of integrated circuits. In spite of extensive efforts, it is not always possible to detect all the functional errors and electrical faults during pre-silicon validation. Post-silicon validation is used to detect design flaws including the escaped functional errors as well as electrical faults. In this tutorial, we will provide a comprehensive coverage of both fundamental concepts and recent advances in post-silicon validation, debug and diagnosis. The tutorial presenters (3 industry experts and 3 faculty members) will provide unique perspectives on both academic research and industrial practices. First, we will discuss various challenges associated with post-silicon validation and debug. Next, we will describe various techniques for automated generation of directed tests to activate both functional errors and electrical faults. We will cover recent advances in observability enhancement through signal selection and low-overhead trace hardware design. We will also describe various state-of-the-art post-silicon debug approaches for modern microprocessors and SoC designs. Next, we will present examples of real-life design failures, and successful debug scenarios in industrial settings. Finally, we will conclude the tutorial with discussion on emerging issues and future directions for successful postsilicon validation and debug.