Study on a new chaotic bitwise dynamical system and its FPGA implementation

In this paper, the structure of a new chaotic bitwise dynamical system （CBDS） is described. Compared to our previous research work, it uses various random bitwise operations instead of only one. The chaotic behavior of CBDS is mathemat- ically proven according to the Devaney＇s definition, and its statistical properties are verified both for uniformity and by a comprehensive, reputed and stringent battery of tests called TestU01. Furthermore, a systematic methodology developing the parallel computations is proposed for FPGA platform-based realization of this CBDS. Experiments finally validate the proposed systematic methodology.