Transition delay fault simulation with parallel critical path back-tracing and 7-valued algebra
A new method is presented for simulating of Transition Delay Faults (TDF) based on the parallel exact critical path tracing for Stuck-at Fault (SAF) analysis and subsequent TDF reasoning. A method is proposed to extend the TDF model, traditionally considered as a class of robustly tested delay fault...
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Veröffentlicht in: | Microprocessors and microsystems 2015-11, Vol.39 (8), p.1130-1138 |
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container_title | Microprocessors and microsystems |
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creator | Kõusaar, Jaak Ubar, Raimund Devadze, Sergei Raik, Jaan |
description | A new method is presented for simulating of Transition Delay Faults (TDF) based on the parallel exact critical path tracing for Stuck-at Fault (SAF) analysis and subsequent TDF reasoning. A method is proposed to extend the TDF model, traditionally considered as a class of robustly tested delay faults, to a class of TDFs with extended detection conditions. Three known fault classes of delay fault sensitization are considered: robust, non-robust and functional sensitization of delay faults. Additionally, a new fourth fault class is introduced, called non-robust functionally sensitized delay fault. A novel fault analysis algorithm based on 7-valued algebra is presented, which delivers the fault coverage for all mentioned four types of TDFs. |
doi_str_mv | 10.1016/j.micpro.2015.05.003 |
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A novel fault analysis algorithm based on 7-valued algebra is presented, which delivers the fault coverage for all mentioned four types of TDFs.</description><subject>7-valued algebra</subject><subject>Algebra</subject><subject>Algorithms</subject><subject>Computer simulation</subject><subject>Critical path fault tracing</subject><subject>Delay</subject><subject>Faults</subject><subject>Microprocessors</subject><subject>Non-robust and functional sensitization</subject><subject>Reasoning</subject><subject>TDF</subject><subject>Transition delay faults</subject><issn>0141-9331</issn><issn>1872-9436</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2015</creationdate><recordtype>article</recordtype><recordid>eNp9kE9LxDAQxYMouK5-Aw89emmdNG3TXgRZ_AcLXtZzmCbTNWu2XZN2xW9v1vUsPBh4_OYN8xi75pBx4NXtJttavfNDlgMvM4gCccJmvJZ52hSiOmUz4AVPGyH4ObsIYQMAJVT5jKmVxz7Y0Q59Ysjhd9Lh5MYk2O3k8Nf-suN7skOPzpFLtI-wRhedaLeoP9LRo7b9OsHeJDLdo5vIJOjW1Hq8ZGcdukBXf3PO3h4fVovndPn69LK4X6ZayHxM864AU5Wy7QC0qEVNTV7pVgqTV43RmtpWYi4KKRoAo5tatmVbUsErMkXkxZzdHHNjDZ8ThVFtbdDkHPY0TEFxWVe8LEohI1ocUe2HEDx1auftFv234qAOfaqNOvapDn0qiILDhbvjGsU39pa8CtpSr8lYT3pUZrD_B_wAYmiBNg</recordid><startdate>20151101</startdate><enddate>20151101</enddate><creator>Kõusaar, Jaak</creator><creator>Ubar, Raimund</creator><creator>Devadze, Sergei</creator><creator>Raik, Jaan</creator><general>Elsevier B.V</general><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>7SP</scope><scope>8FD</scope><scope>F28</scope><scope>FR3</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope></search><sort><creationdate>20151101</creationdate><title>Transition delay fault simulation with parallel critical path back-tracing and 7-valued algebra</title><author>Kõusaar, Jaak ; Ubar, Raimund ; Devadze, Sergei ; Raik, Jaan</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c372t-2f40d657bf00c3838e926cb73d269dccebb7a23473900dc987b5b5e416ed43833</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2015</creationdate><topic>7-valued algebra</topic><topic>Algebra</topic><topic>Algorithms</topic><topic>Computer simulation</topic><topic>Critical path fault tracing</topic><topic>Delay</topic><topic>Faults</topic><topic>Microprocessors</topic><topic>Non-robust and functional sensitization</topic><topic>Reasoning</topic><topic>TDF</topic><topic>Transition delay faults</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Kõusaar, Jaak</creatorcontrib><creatorcontrib>Ubar, Raimund</creatorcontrib><creatorcontrib>Devadze, Sergei</creatorcontrib><creatorcontrib>Raik, Jaan</creatorcontrib><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><jtitle>Microprocessors and microsystems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Kõusaar, Jaak</au><au>Ubar, Raimund</au><au>Devadze, Sergei</au><au>Raik, Jaan</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Transition delay fault simulation with parallel critical path back-tracing and 7-valued algebra</atitle><jtitle>Microprocessors and microsystems</jtitle><date>2015-11-01</date><risdate>2015</risdate><volume>39</volume><issue>8</issue><spage>1130</spage><epage>1138</epage><pages>1130-1138</pages><issn>0141-9331</issn><eissn>1872-9436</eissn><abstract>A new method is presented for simulating of Transition Delay Faults (TDF) based on the parallel exact critical path tracing for Stuck-at Fault (SAF) analysis and subsequent TDF reasoning. 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subjects | 7-valued algebra Algebra Algorithms Computer simulation Critical path fault tracing Delay Faults Microprocessors Non-robust and functional sensitization Reasoning TDF Transition delay faults |
title | Transition delay fault simulation with parallel critical path back-tracing and 7-valued algebra |
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