Gate-level body biasing for subthreshold logic circuits: analytical modeling and design guidelines

Summary Gate‐level body biasing provides an attractive solution to increase speed and robustness against process and temperature variations while maintaining energy efficiency. In this paper, the behavior of basic logic gates, designed according to the proposed design technique, is analytically exam...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:International journal of circuit theory and applications 2015-11, Vol.43 (11), p.1523-1540
Hauptverfasser: Albano, D., Lanuzza, M., Taco, R., Crupi, F.
Format: Artikel
Sprache:eng
Schlagworte:
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!