Gate-level body biasing for subthreshold logic circuits: analytical modeling and design guidelines
Summary Gate‐level body biasing provides an attractive solution to increase speed and robustness against process and temperature variations while maintaining energy efficiency. In this paper, the behavior of basic logic gates, designed according to the proposed design technique, is analytically exam...
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Veröffentlicht in: | International journal of circuit theory and applications 2015-11, Vol.43 (11), p.1523-1540 |
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Hauptverfasser: | , , , |
Format: | Artikel |
Sprache: | eng |
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