Gate-level body biasing for subthreshold logic circuits: analytical modeling and design guidelines

Summary Gate‐level body biasing provides an attractive solution to increase speed and robustness against process and temperature variations while maintaining energy efficiency. In this paper, the behavior of basic logic gates, designed according to the proposed design technique, is analytically examined with the main purpose of furnishing important guidelines to design efficient subthreshold digital circuits. Our modeling has been fully validated by comparing the predicted results with SPICE simulations performed for a commercial 45‐nm complementary metal oxide semiconductor technology. Considering process, temperature and loading capacitance variations, the delay of an inverter is predicted with a maximum error lower than 16.5%. Even better results are obtained when our modeling is applied to more complex logic gates. Under process, loading capacitance and temperature variations, the delay of NAND2 and NOR2 logic gates is always predicted with an error below 10%. Good agreement between the predicted and simulated results makes our modeling a valuable support during the circuit design phase. Copyright © 2014 John Wiley & Sons, Ltd. In this work, the gate‐level body biasing technique recently introduced by our group is analytically justified through an accurate analysis on the inverter gate, NAND2 gate and NOR2 gate. The proposed modeling has been fully validated by comparing the results predicted by the theoretical model with Cadence Spectre simulations performed for a commercial 45‐nm complementary metal oxide semiconductor technology on different process corners and temperatures. Good agreement between the predicted and simulated results confirms the validity of the proposed design guidelines as a very useful aid to the design of high‐speed subthreshold logic gates.