Comparison between N sub(2) and O sub(2) anneals on the integrity of an Al sub(2)O sub(3)/Si sub(3)N sub(4)/SiO sub(2)/Si memory gate stack

In this paper the endurance characteristics and trap generation are investigated to study the effects of different post-deposition anneals (PDAs) on the integrity of an Al sub(2)O sub(3)/Si sub(3)N sub(4)/SiO sub(2)/Si memory gate stack. The flat-band voltage (V sub(fb)) turnarounds are observed in both the programmed and erased states of the N sub(2)-PDA device. In contrast, this turnaround is observed only in the erased state of the O sub(2)-PDA device. The V sub(fb) in the programmed state of the O sub(2)-PDA device keeps increasing with increasing program/erase (P/E) cycles. Through the analyses of endurance characteristics and the low voltage round-trip current transients, it is concluded that in both kinds of device there are an unknown type of pre-existing characteristic deep traps and P/E stress-induced positive oxide charges. In the O sub(2)-PDA device two extra types of trap are also found: the pre-existing border traps and the P/E stress-induced negative traps. Based on these four types of defects we can explain the endurance characteristics of two kinds of device. The switching property of pre-existing characteristic deep traps is also discussed.