Direct Digital Frequency Synthesizer Simulation and Design by means of Quartus-ModelSim

A new full simulation, design and verification of a Direct Digital Frequency Synthesizer (DDFS), utilizing only one quarter of a given sinusoidal wave, are presented in this study. A reduction in the size of the LUT is accomplished as the new design requires storing only a quarter of the sine wave. The Register Transfer Level (RTL) and the Gate level is implemented by the Quartus II. The Quartus II will then invoke the ModelSim Altera software to simulate the output. The DDFS consists of three major models, mainly a Phase Accumulator (PA), a Phase Register and a Look Up Table (LUT). All of the mentioned models are realized by a Verilog code. The spurious free dynamic range is achieved with a value of -73 dB using a 16 bit phase accumulator. The proposed design is verified through the application of different input frequencies and obtained results showed that output frequency is directly proportional to the tuning input frequency.