Novel N-hit single event transient mitigation technique via open guard transistor in 65 nm bulk CMOS process

In this paper, we proposed a new n-channel MOS single event transient （SET） mitigation technique, which is called the open guard transistor （OGT） technique. This hardening scheme is compared with several classical n-channel MOS hardening struc- tures through 3-D TCAD simulations. The results show that this scheme presents about 35% improvements over the unhard- ened scheme for mitigating the SET pulse, and its upgrade, the 2-fringe scheme, takes on even more than 50% improvements over the unhardened one. This makes significant sense for the semi-conductor device reliability.