A front-end chip development for the sLHC CMS Silicon Strip Tracker

The FEAFS chip has been designed for the upgrades of the CMS Silicon Strip Tracker, which is planned in view of the LHC high luminosity upgrade. Its primary function is to provide a 40MHz selective readout of particle hits that will be used for the generation of the 100 kHz hardware trigger of the experiment within a latency of 6.4 mu s. To achieve this goal, the chip identifies clusters of limited number of activated strips and correlated in position, in a given window, in two closely superimposed sensors connected to the same chip. Finally, trigger and DAQ data are transmitted off detector via a common link. The FEAFS chip has been developed in IBM 0.13 mu m technology. This paper presents the design of the chip and test results.