A current monitoring technique for I sub(DDQ) testing in digital integrated circuits

Although IDDQ testing has become a widely accepted defect detection technique in CMOS ICs, its effectiveness in nanometer technologies is threatened by the increased leakage current variations. In this paper, a current monitoring technique that overcomes the current variations problem in I sub(DDQ) testing is proposed. According to this, a core is partitioned into two subcircuits and the intrinsic leakage current of the one subcircuit is used to control the leakage current at the I sub(DDQ) sensing node of the other and vice-versa during test application. This way process related leakage current variations are taken into account and small defective currents turn to be detectable according to the needs of modern nanometer technologies. Additionally, a Built-In Current Sensor is presented, which exploits the proposed technique and experimental results are illustrated by its application on a fabricated chip.