Investigation of multi-level-cell and SET operations on super-lattice phase change memories

This paper gives the optimum SET pulse with the investigation on SET current delay and the multi-level-cell (MLC) operation for super-lattice phase change memories (SL-PCMs). From the investigation, the voltage, or the electric field triggers RESET/SET transition of SL-PCM. The induced energy is als...

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Veröffentlicht in:Japanese Journal of Applied Physics 2014-04, Vol.53 (4S), p.4-1-04ED02-8
Hauptverfasser: Egami, Toru, Johguchi, Koh, Yamazaki, Senju, Takeuchi, Ken
Format: Artikel
Sprache:eng
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Zusammenfassung:This paper gives the optimum SET pulse with the investigation on SET current delay and the multi-level-cell (MLC) operation for super-lattice phase change memories (SL-PCMs). From the investigation, the voltage, or the electric field triggers RESET/SET transition of SL-PCM. The induced energy is also essential for changing the resistance state. In this paper, the MLC operation is also verified with RESET pulse, 1-step SET pulse and 2-step SET pulse. The measurement results indicate the 2-step SET pulse is the best for the MLC function, which realizes the precise resistance controlling. Additionally, the retention-time is measured to evaluate the reliability of MLC SL-PCM. The features of SL-PCM are not only small RESET/SET current, but also MLC operation and the SL-PCM technology provides a potential for next generation non-volatile memories.
ISSN:0021-4922
1347-4065
DOI:10.7567/JJAP.53.04ED02