Fast Edge Detection Architecture using Different Levels of Parallelism on a FPGA

Implementing edge detection techniques on a FPGA has recently become more popular since it benefits high speed which is desired for real-time applications. This work presents a fast FPGAbased architecture for first order derivative edge detection methods. Fast pipeline-based architectures are presented which are able to perform edge detection using different levels of parallelism to accelerate the process. This acceleration includes applying parallelism over convolution masks, edge detection modules and image intensity values. Two different edge detection architectures are proposed called one-way and two-way parallel methods. The architectures are implemented using Verilog HDL for a typical image and we synthesized them for Cyclone IV FPGA. Experimental results show the speed-up near to 460 and 920 for one-way and two-way parallel architectures.