Double-sampled wideband delta–sigma ADCs with shifted loop delays
A novel double-sampled wideband delta–sigma modulator topology with shifted loop delays is proposed. Compared with the conventional double-sampled modulator, this analogue-to-digital converter (ADC) implements the inherent quantisation delay by shifting one loop delay from the last integrator to the...
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| Veröffentlicht in: | Electronics letters 2014-05, Vol.50 (11), p.794-795 |
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| container_title | Electronics letters |
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| creator | Meng, X Temes, G.C |
| description | A novel double-sampled wideband delta–sigma modulator topology with shifted loop delays is proposed. Compared with the conventional double-sampled modulator, this analogue-to-digital converter (ADC) implements the inherent quantisation delay by shifting one loop delay from the last integrator to the quantiser, and it relaxes the critical timing for dynamic element matching (DEM) by shifting the loop delay from the first integrator to the feedback path. In addition, by inserting one more delay in the signal path, the proposed modulator retains the low-distortion property. To verify the effectiveness of the proposed topology, a second-order double-sampled delta–sigma modulator is analysed and simulated. |
| doi_str_mv | 10.1049/el.2014.0994 |
| format | Article |
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Compared with the conventional double-sampled modulator, this analogue-to-digital converter (ADC) implements the inherent quantisation delay by shifting one loop delay from the last integrator to the quantiser, and it relaxes the critical timing for dynamic element matching (DEM) by shifting the loop delay from the first integrator to the feedback path. In addition, by inserting one more delay in the signal path, the proposed modulator retains the low-distortion property. To verify the effectiveness of the proposed topology, a second-order double-sampled delta–sigma modulator is analysed and simulated.</description><identifier>ISSN: 0013-5194</identifier><identifier>ISSN: 1350-911X</identifier><identifier>EISSN: 1350-911X</identifier><identifier>DOI: 10.1049/el.2014.0994</identifier><identifier>CODEN: ELLEAK</identifier><language>eng</language><publisher>Stevenage: The Institution of Engineering and Technology</publisher><subject>analog‐digital conversion ; Applied sciences ; circuit feedback ; Circuit properties ; Circuits and systems ; critical timing ; Delay ; delays ; delta‐sigma ADC ; delta‐sigma modulation ; Discrete element method ; double sampled ADC ; dynamic element matching ; Electric, optical and optoelectronic circuits ; Electronic circuits ; Electronics ; Exact sciences and technology ; Integrators ; Modulators ; quantisation (signal) ; quantisation delay ; shifted loop delay ; Signal convertors ; Simulation ; Time measurements ; timing ; Topology ; Wideband ; wideband ADC</subject><ispartof>Electronics letters, 2014-05, Vol.50 (11), p.794-795</ispartof><rights>The Institution of Engineering and Technology</rights><rights>2020 The Institution of Engineering and Technology</rights><rights>2015 INIST-CNRS</rights><rights>Copyright The Institution of Engineering & Technology May 22, 2014</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c4720-505ac93417560f6e8ee5a26c167ea96893189b6f3817cf733100107e74b640c93</citedby><cites>FETCH-LOGICAL-c4720-505ac93417560f6e8ee5a26c167ea96893189b6f3817cf733100107e74b640c93</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://onlinelibrary.wiley.com/doi/pdf/10.1049%2Fel.2014.0994$$EPDF$$P50$$Gwiley$$H</linktopdf><linktohtml>$$Uhttps://onlinelibrary.wiley.com/doi/full/10.1049%2Fel.2014.0994$$EHTML$$P50$$Gwiley$$H</linktohtml><link.rule.ids>314,780,784,1417,11562,27924,27925,45574,45575,46052,46476</link.rule.ids><linktorsrc>$$Uhttps://onlinelibrary.wiley.com/doi/abs/10.1049%2Fel.2014.0994$$EView_record_in_Wiley-Blackwell$$FView_record_in_$$GWiley-Blackwell</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=28496005$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Meng, X</creatorcontrib><creatorcontrib>Temes, G.C</creatorcontrib><title>Double-sampled wideband delta–sigma ADCs with shifted loop delays</title><title>Electronics letters</title><description>A novel double-sampled wideband delta–sigma modulator topology with shifted loop delays is proposed. Compared with the conventional double-sampled modulator, this analogue-to-digital converter (ADC) implements the inherent quantisation delay by shifting one loop delay from the last integrator to the quantiser, and it relaxes the critical timing for dynamic element matching (DEM) by shifting the loop delay from the first integrator to the feedback path. In addition, by inserting one more delay in the signal path, the proposed modulator retains the low-distortion property. To verify the effectiveness of the proposed topology, a second-order double-sampled delta–sigma modulator is analysed and simulated.</description><subject>analog‐digital conversion</subject><subject>Applied sciences</subject><subject>circuit feedback</subject><subject>Circuit properties</subject><subject>Circuits and systems</subject><subject>critical timing</subject><subject>Delay</subject><subject>delays</subject><subject>delta‐sigma ADC</subject><subject>delta‐sigma modulation</subject><subject>Discrete element method</subject><subject>double sampled ADC</subject><subject>dynamic element matching</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electronic circuits</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Integrators</subject><subject>Modulators</subject><subject>quantisation (signal)</subject><subject>quantisation delay</subject><subject>shifted loop delay</subject><subject>Signal convertors</subject><subject>Simulation</subject><subject>Time measurements</subject><subject>timing</subject><subject>Topology</subject><subject>Wideband</subject><subject>wideband ADC</subject><issn>0013-5194</issn><issn>1350-911X</issn><issn>1350-911X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2014</creationdate><recordtype>article</recordtype><sourceid>AFKRA</sourceid><sourceid>AZQEC</sourceid><sourceid>BENPR</sourceid><sourceid>CCPQU</sourceid><sourceid>DWQXO</sourceid><sourceid>GNUQQ</sourceid><recordid>eNp90MtqGzEUBmARGohJsssDGNpCFx3nnNFttEwd5wID2aTQndDMnIlVZM90ZBO8yzv0DfMkkXFITQhdCaHv_Pw6jJ0hTBCEOacwyQHFBIwRB2yEXEJmEH99YiMA5JlEI47YaYy-SgyFAoEjNr3s1lWgLLpFH6gZP_qGKrdsxg2FlXt--hv9w8KNLy6nMb2t5uM49-0qwdB1_Ra5TTxhh60LkU5fz2P282p2P73Jyrvr2-lFmdVC55BJkK42XKCWClpFBZF0uapRaXJGFYZjYSrV8gJ13WrOMfUGTVpUSkCaPGbfdrn90P1ZU1zZhY81heCW1K2jTUGoQCuFiX5-R39362GZ2lmUAo3huSqS-r5T9dDFOFBr-8Ev3LCxCHa7VEvBbpdqt0tN_OtrqIu1C-3glrWPbzN5IYwCkMnJnXv0gTb_zbSzssx_XKWrhn__87Tf9-MqXz6gs3IvuW9a_gLJE5zJ</recordid><startdate>20140522</startdate><enddate>20140522</enddate><creator>Meng, X</creator><creator>Temes, G.C</creator><general>The Institution of Engineering and Technology</general><general>Institution of Engineering and Technology</general><general>John Wiley & Sons, Inc</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>8FE</scope><scope>8FG</scope><scope>ABJCF</scope><scope>AFKRA</scope><scope>ARAPS</scope><scope>AZQEC</scope><scope>BENPR</scope><scope>BGLVJ</scope><scope>CCPQU</scope><scope>DWQXO</scope><scope>GNUQQ</scope><scope>HCIFZ</scope><scope>JQ2</scope><scope>K7-</scope><scope>L6V</scope><scope>M7S</scope><scope>P5Z</scope><scope>P62</scope><scope>PQEST</scope><scope>PQQKQ</scope><scope>PQUKI</scope><scope>PRINS</scope><scope>PTHSS</scope><scope>7SC</scope><scope>7SP</scope><scope>8FD</scope><scope>F28</scope><scope>FR3</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope></search><sort><creationdate>20140522</creationdate><title>Double-sampled wideband delta–sigma ADCs with shifted loop delays</title><author>Meng, X ; Temes, G.C</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c4720-505ac93417560f6e8ee5a26c167ea96893189b6f3817cf733100107e74b640c93</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2014</creationdate><topic>analog‐digital conversion</topic><topic>Applied sciences</topic><topic>circuit feedback</topic><topic>Circuit properties</topic><topic>Circuits and systems</topic><topic>critical timing</topic><topic>Delay</topic><topic>delays</topic><topic>delta‐sigma ADC</topic><topic>delta‐sigma modulation</topic><topic>Discrete element method</topic><topic>double sampled ADC</topic><topic>dynamic element matching</topic><topic>Electric, optical and optoelectronic circuits</topic><topic>Electronic circuits</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Integrators</topic><topic>Modulators</topic><topic>quantisation (signal)</topic><topic>quantisation delay</topic><topic>shifted loop delay</topic><topic>Signal convertors</topic><topic>Simulation</topic><topic>Time measurements</topic><topic>timing</topic><topic>Topology</topic><topic>Wideband</topic><topic>wideband ADC</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Meng, X</creatorcontrib><creatorcontrib>Temes, G.C</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>ProQuest SciTech Collection</collection><collection>ProQuest Technology Collection</collection><collection>Materials Science & Engineering Collection</collection><collection>ProQuest Central UK/Ireland</collection><collection>Advanced Technologies & Aerospace Collection</collection><collection>ProQuest Central Essentials</collection><collection>ProQuest Central</collection><collection>Technology Collection</collection><collection>ProQuest One Community College</collection><collection>ProQuest Central Korea</collection><collection>ProQuest Central Student</collection><collection>SciTech Premium Collection</collection><collection>ProQuest Computer Science Collection</collection><collection>Computer Science Database</collection><collection>ProQuest Engineering Collection</collection><collection>Engineering Database</collection><collection>Advanced Technologies & Aerospace Database</collection><collection>ProQuest Advanced Technologies & Aerospace Collection</collection><collection>ProQuest One Academic Eastern Edition (DO NOT USE)</collection><collection>ProQuest One Academic</collection><collection>ProQuest One Academic UKI Edition</collection><collection>ProQuest Central China</collection><collection>Engineering Collection</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><jtitle>Electronics letters</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Meng, X</au><au>Temes, G.C</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Double-sampled wideband delta–sigma ADCs with shifted loop delays</atitle><jtitle>Electronics letters</jtitle><date>2014-05-22</date><risdate>2014</risdate><volume>50</volume><issue>11</issue><spage>794</spage><epage>795</epage><pages>794-795</pages><issn>0013-5194</issn><issn>1350-911X</issn><eissn>1350-911X</eissn><coden>ELLEAK</coden><abstract>A novel double-sampled wideband delta–sigma modulator topology with shifted loop delays is proposed. Compared with the conventional double-sampled modulator, this analogue-to-digital converter (ADC) implements the inherent quantisation delay by shifting one loop delay from the last integrator to the quantiser, and it relaxes the critical timing for dynamic element matching (DEM) by shifting the loop delay from the first integrator to the feedback path. In addition, by inserting one more delay in the signal path, the proposed modulator retains the low-distortion property. To verify the effectiveness of the proposed topology, a second-order double-sampled delta–sigma modulator is analysed and simulated.</abstract><cop>Stevenage</cop><pub>The Institution of Engineering and Technology</pub><doi>10.1049/el.2014.0994</doi><tpages>2</tpages><oa>free_for_read</oa></addata></record> |
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| source | Wiley-Blackwell Open Access Titles |
| subjects | analog‐digital conversion Applied sciences circuit feedback Circuit properties Circuits and systems critical timing Delay delays delta‐sigma ADC delta‐sigma modulation Discrete element method double sampled ADC dynamic element matching Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology Integrators Modulators quantisation (signal) quantisation delay shifted loop delay Signal convertors Simulation Time measurements timing Topology Wideband wideband ADC |
| title | Double-sampled wideband delta–sigma ADCs with shifted loop delays |
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