Double-sampled wideband delta–sigma ADCs with shifted loop delays

A novel double-sampled wideband delta–sigma modulator topology with shifted loop delays is proposed. Compared with the conventional double-sampled modulator, this analogue-to-digital converter (ADC) implements the inherent quantisation delay by shifting one loop delay from the last integrator to the quantiser, and it relaxes the critical timing for dynamic element matching (DEM) by shifting the loop delay from the first integrator to the feedback path. In addition, by inserting one more delay in the signal path, the proposed modulator retains the low-distortion property. To verify the effectiveness of the proposed topology, a second-order double-sampled delta–sigma modulator is analysed and simulated.