A high-speed offset cancelling distributed sample-and-hold architecture for flash A/D converters

A 6-bit high-speed analog-to-digital converter was implemented utilizing a novel distributed sample-and-hold architecture capable of sampling and subtracting the input preamplifier's offset. This architecture offers substantial improvement in the high-speed operation of the converter. Compared...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:Microelectronics 2013-12, Vol.44 (12), p.1123-1131
Hauptverfasser: Mountrichas, L., Siskos, S.
Format: Artikel
Sprache:eng
Schlagworte:
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:A 6-bit high-speed analog-to-digital converter was implemented utilizing a novel distributed sample-and-hold architecture capable of sampling and subtracting the input preamplifier's offset. This architecture offers substantial improvement in the high-speed operation of the converter. Compared to the prior-art, the effective number of bits improves 0.8bit. The spurious free dynamic range improvement is over 12dB. In addition the implemented technique uses half the number of capacitors compared to similar designs. The converter achieves over 5.2bit resolution up to the Nyquist input signal frequency. A simple but effective design methodology is also presented.
ISSN:1879-2391
0026-2692
1879-2391
DOI:10.1016/j.mejo.2013.06.016