A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS
This paper presents a 40 Gb/s serializer IC in 65 nm bulk CMOS technology. The IC has an SFI5.2-compliant 10 Gb/s input interface and supports two different output modes, single 40 Gb/s for OC-768 VSR and dual 20 Gb/s for DQPSK. The IC is evaluated on a PCB and error-free operation is confirmed. The...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 2009-12, Vol.44 (12), p.3580-3589 |
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| container_end_page | 3589 |
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| container_issue | 12 |
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| container_title | IEEE journal of solid-state circuits |
| container_volume | 44 |
| creator | Kanda, K. Tamura, H. Yamamoto, T. Matsubara, S. Kibune, M. Doi, Y. Shibasaki, T. Tzartzanis, N. Kristensson, A. Parikh, S. Ide, S. Tsunoda, Y. Yamabana, T. Sugawara, M. Kuwata, N. Ikeuchi, T. Ogawa, J. Walker, W.W. |
| description | This paper presents a 40 Gb/s serializer IC in 65 nm bulk CMOS technology. The IC has an SFI5.2-compliant 10 Gb/s input interface and supports two different output modes, single 40 Gb/s for OC-768 VSR and dual 20 Gb/s for DQPSK. The IC is evaluated on a PCB and error-free operation is confirmed. The chip consumes 1.8 W for the 40 G mode, and 1.6 W for the 20 G mode from 1.2 V and 3.3 V power supplies. |
| doi_str_mv | 10.1109/JSSC.2009.2031030 |
| format | Article |
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The IC has an SFI5.2-compliant 10 Gb/s input interface and supports two different output modes, single 40 Gb/s for OC-768 VSR and dual 20 Gb/s for DQPSK. The IC is evaluated on a PCB and error-free operation is confirmed. The chip consumes 1.8 W for the 40 G mode, and 1.6 W for the 20 G mode from 1.2 V and 3.3 V power supplies.</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.2009.2031030</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>40 Gb/s ; 65 nm CMOS ; Chips ; Circuit boards ; Circuit testing ; Circuits ; CMOS ; CMOS integrated circuits ; CMOS technology ; Consumption ; DQPSK ; Error-free operation ; Integrated circuits ; Laboratories ; OC-768 ; Optical fiber networks ; Optical receivers ; Paper technology ; Power supplies ; Printed circuits ; SFI5.2 ; Transponders</subject><ispartof>IEEE journal of solid-state circuits, 2009-12, Vol.44 (12), p.3580-3589</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2009</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c356t-231c56fdbafec350edb097a717d30d13f26d8a0486efd45541adeb292f4ce5e93</citedby><cites>FETCH-LOGICAL-c356t-231c56fdbafec350edb097a717d30d13f26d8a0486efd45541adeb292f4ce5e93</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5342358$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5342358$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Kanda, K.</creatorcontrib><creatorcontrib>Tamura, H.</creatorcontrib><creatorcontrib>Yamamoto, T.</creatorcontrib><creatorcontrib>Matsubara, S.</creatorcontrib><creatorcontrib>Kibune, M.</creatorcontrib><creatorcontrib>Doi, Y.</creatorcontrib><creatorcontrib>Shibasaki, T.</creatorcontrib><creatorcontrib>Tzartzanis, N.</creatorcontrib><creatorcontrib>Kristensson, A.</creatorcontrib><creatorcontrib>Parikh, S.</creatorcontrib><creatorcontrib>Ide, S.</creatorcontrib><creatorcontrib>Tsunoda, Y.</creatorcontrib><creatorcontrib>Yamabana, T.</creatorcontrib><creatorcontrib>Sugawara, M.</creatorcontrib><creatorcontrib>Kuwata, N.</creatorcontrib><creatorcontrib>Ikeuchi, T.</creatorcontrib><creatorcontrib>Ogawa, J.</creatorcontrib><creatorcontrib>Walker, W.W.</creatorcontrib><title>A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>This paper presents a 40 Gb/s serializer IC in 65 nm bulk CMOS technology. The IC has an SFI5.2-compliant 10 Gb/s input interface and supports two different output modes, single 40 Gb/s for OC-768 VSR and dual 20 Gb/s for DQPSK. The IC is evaluated on a PCB and error-free operation is confirmed. The chip consumes 1.8 W for the 40 G mode, and 1.6 W for the 20 G mode from 1.2 V and 3.3 V power supplies.</description><subject>40 Gb/s</subject><subject>65 nm CMOS</subject><subject>Chips</subject><subject>Circuit boards</subject><subject>Circuit testing</subject><subject>Circuits</subject><subject>CMOS</subject><subject>CMOS integrated circuits</subject><subject>CMOS technology</subject><subject>Consumption</subject><subject>DQPSK</subject><subject>Error-free operation</subject><subject>Integrated circuits</subject><subject>Laboratories</subject><subject>OC-768</subject><subject>Optical fiber networks</subject><subject>Optical receivers</subject><subject>Paper technology</subject><subject>Power supplies</subject><subject>Printed circuits</subject><subject>SFI5.2</subject><subject>Transponders</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2009</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNp9kU1Lw0AQhhdRsFZ_gHhZPIiXtDv7kWyOJdoaqVSIordlk0w0JU11Nz3orzelxYMHLzPM8LwDw0PIObARAIvH91mWjDhjcV8EMMEOyACU0gFE4vWQDBgDHcQ9cExOvF_2o5QaBuRxQrO6fWswkIzO8rGnNxvbBHw_ZOhq29Tf6Gia0Je6e6fZNA3UiNO07dBVtkBatzRUtF3R5GGRnZKjyjYez_Z9SJ6nt0_JXTBfzNJkMg8KocIu4AIKFVZlbivsNwzLnMWRjSAqBStBVDwstWVSh1iVUikJtsScx7ySBSqMxZBc7e5-uPXnBn1nVrUvsGlsi-uNNyIUMpRC9-D1vyCEESjQKtqil3_Q5Xrj2v4NE0PEecQ06yHYQYVbe--wMh-uXln3ZYCZrQuzdWG2LszeRZ-52GVqRPzllZBcKC1-AOYDf2c</recordid><startdate>20091201</startdate><enddate>20091201</enddate><creator>Kanda, K.</creator><creator>Tamura, H.</creator><creator>Yamamoto, T.</creator><creator>Matsubara, S.</creator><creator>Kibune, M.</creator><creator>Doi, Y.</creator><creator>Shibasaki, T.</creator><creator>Tzartzanis, N.</creator><creator>Kristensson, A.</creator><creator>Parikh, S.</creator><creator>Ide, S.</creator><creator>Tsunoda, Y.</creator><creator>Yamabana, T.</creator><creator>Sugawara, M.</creator><creator>Kuwata, N.</creator><creator>Ikeuchi, T.</creator><creator>Ogawa, J.</creator><creator>Walker, W.W.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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The IC has an SFI5.2-compliant 10 Gb/s input interface and supports two different output modes, single 40 Gb/s for OC-768 VSR and dual 20 Gb/s for DQPSK. The IC is evaluated on a PCB and error-free operation is confirmed. The chip consumes 1.8 W for the 40 G mode, and 1.6 W for the 20 G mode from 1.2 V and 3.3 V power supplies.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/JSSC.2009.2031030</doi><tpages>10</tpages></addata></record> |
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| identifier | ISSN: 0018-9200 |
| ispartof | IEEE journal of solid-state circuits, 2009-12, Vol.44 (12), p.3580-3589 |
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| language | eng |
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| subjects | 40 Gb/s 65 nm CMOS Chips Circuit boards Circuit testing Circuits CMOS CMOS integrated circuits CMOS technology Consumption DQPSK Error-free operation Integrated circuits Laboratories OC-768 Optical fiber networks Optical receivers Paper technology Power supplies Printed circuits SFI5.2 Transponders |
| title | A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS |
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