A 3[Formula Omitted]5-Gb/s Multilane Low-Power 0.18-[Formula Omitted] CMOS Pseudorandom Bit Sequence Generator

A 3[Formula Omitted]5-Gb/s Multilane Low-Power 0.18-[Formula Omitted] CMOS Pseudorandom Bit Sequence Generator

In order to reduce the power consumption, a quarter-clock rate linear feedback shift register (LFSR) core in a power-efficient parallel architecture has been implemented to minimize the use of power-hungry, high-speed circuitry.

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Bibliographische Detailangaben
Veröffentlicht in:IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2008-05, Vol.55 (5), p.432
Hauptverfasser: Sham, Kin-Joe, Bommalingaiahnapallya, S, Ahmadi, M.R, Harjani, R
Format: Artikel
Sprache:eng
Schlagworte:
Channels
CMOS
Design
Design engineering
Generators
High speed
Lanes
Logic
Prototypes
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Beschreibung
Zusammenfassung:In order to reduce the power consumption, a quarter-clock rate linear feedback shift register (LFSR) core in a power-efficient parallel architecture has been implemented to minimize the use of power-hungry, high-speed circuitry.
ISSN:1549-7747
1558-3791
DOI:10.1109/TCSII.2007.912696