A 94-mW, 100-MS/s, 12-bit pipeline ADC for multi-standard TV demodulation applications

This paper presents the design and implementation of a 12-bit Analog-to-Digital Converter (ADC) for multi-standard TV demodulation applications. The ADC was fabricated in a standard digital 90-nm CMOS process and it is built by means of a front-end sample-and-hold and a cascade of 10 pipeline stages with 1.5-bits resolution. Performance of 60-dB signal-to-noise-ratio and 68-dB spurious-free-dynamic-range is obtained without calibration at 100-MS/s with a 1-V P-P input signal swing. The occupied silicon area is 0.5-mm 2 ; and the power consumption of 94-mW from a 1.2-V supply.