ReSSIM：a mixed-level simulator for dynamic coarse-grained reconfigurable processor

This paper proposes a mixed-level simulator for dynamic coarse-grained reconfigurable processor（CGRP）,called ReSSIM（reconfigurable system simulation implementation mechanism）,and the corresponding simulation tool-chain,including task compiler,profiler and debugger.A generic modeling methodology supporting convenient extension of on-chip modules is also proposed.In order to explore the details of the interested modules while maintaining reasonable simulation speed,RCA（reconfigurable computing array）,the key reconfigurable device in ReSSIM,is modeled on cycle-accurate level,while the other modules are modeled on transaction level.The typical parameters of RCA are scalable and adjustable,which helps the architects to explore the massive details of the reconfigurable device.Experiment shows that simulation speedup achieved ranges from 9.26× to 18.39× compared with VCS（Synopsys verilog compiler simulator） when running three computingintensive kernel tasks of H.264 decoding algorithm-IDCT（inverse discrete cosine transform）,deblocking and MC-chroma（motion compensation）.Simulation speed for a set of real applications,such as MPEG4,G.729 and EFR,is 35× slower than the corresponding native executions（i.e.measured from the real chip）.And the relative simulation errors are 11% less than the measured IPC（instructions per cycle） of the real chip.