Border-Trap Characterization in High- \kappa Strained-Si MOSFETs

Border-Trap Characterization in High- \kappa Strained-Si MOSFETs

In this letter, we focus on the border-trap characterization of TaN/HfO 2 /Si and TaN/HfO 2 /strained-Si/Si 0.8 Ge 0.2 n-channel MOSFET devices. The equivalent oxide thickness for the gate dielectrics is 2 nm. Drain-current hysteresis method is used to characterize the border traps, and it is found...

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Veröffentlicht in:IEEE electron device letters 2007-08, Vol.28 (8), p.731-733
Hauptverfasser: Debabrata Maji, Duttagupta, S.P., Rao, V.R., Chia Ching Yeo, Byung-Jin Cho
Format: Artikel
Sprache:eng
Schlagworte:
1/f noise
Applied sciences
Border traps
Borders
charge pumping
Charge pumps
CMOS technology
Devices
Dielectrics
Electronics
Equivalence
Exact sciences and technology
Fabrication
Frequency
Hafnium oxide
Hysteresis
interface trapping
MOSFETs
Oxides
Pulse measurements
Rapid thermal annealing
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Silicon
strained-Si
Transistors
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Zusammenfassung:In this letter, we focus on the border-trap characterization of TaN/HfO 2 /Si and TaN/HfO 2 /strained-Si/Si 0.8 Ge 0.2 n-channel MOSFET devices. The equivalent oxide thickness for the gate dielectrics is 2 nm. Drain-current hysteresis method is used to characterize the border traps, and it is found that border traps are higher in the case of high-kappa films on strained- Si/Si 0.8 Ge 0.2 .These results are also verified by the 1/f-noise measurements. Possible reasons for the degraded interface quality of high-kappa films on strained-Si are also proposed.
ISSN:0741-3106
1558-0563
DOI:10.1109/LED.2007.902086