System-on-chip testability using LSSD scan structures

A technology-independent test synthesis tool extends the basic level-sensitive scan design (LSSD) boundary scan methodology. It reuses functional storage elements wherever possible and introduces minimal test logic overhead and delay.

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Bibliographische Detailangaben
Veröffentlicht in:	IEEE design & test of computers 2001-05, Vol.18 (3), p.83-97
Hauptverfasser:	Zarrineh, K., Upadhyaya, S.J., Chickermane, V.
Format:	Artikel
Sprache:	eng
Schlagworte:	Automatic testing Boundaries Clocks Delay Design engineering Flip-flops Logic testing Master-slave Microelectronics Protocols Reuse Shift registers Synthesis System on chip System testing System-on-a-chip Testability
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Beschreibung
Zusammenfassung:	A technology-independent test synthesis tool extends the basic level-sensitive scan design (LSSD) boundary scan methodology. It reuses functional storage elements wherever possible and introduces minimal test logic overhead and delay.
ISSN:	0740-7475 2168-2356 1558-1918 2168-2364
DOI:	10.1109/54.922805