PROCESSING ENCRYPTED SCALAR/VECTOR DATA ON UNIFIED DATAPATH

This paper extends our proposed processor VVSHP by encryption/decryption/key-expansion units based on RC5 cryptographic algorithm to process encrypted scalar/vector data. VVSHP has a modified five-stage pipeline for executing multi-scalar/vector instructions by fetching 128-bit VLIW instruction, decoding/reading operands of four individual instructions, executing four scalar/vector operations, accessing memory to load/store 128-bit data, and writing back up to four 32-bit results. The key-expansion unit accepts 96-bit user's secrete key to generate the expanded key array needed for the encryption and decryption units. By extending the execute stage with encryption unit and memory access stage by decryption unit, CryptoVVSHP can process encrypted 32-bit data with lengths varying from 1 to 256. Thus, before storing into memory, scalar/vector data are encrypted, and after loading from memory, scalar/vector data are decrypted. Therefore, data only ever exists as plaintext inside the processor itself. The design of the proposed CryptoVVSHP processor is implemented using VHDL targeting the Xilinx FPGA Virtex-5, XC5VLX110T-3FF1136 device. The number of LUT flip-flop pairs used for implementing CryptoVVSHP is 109737, where the numbers of unused flip-flops, unused LUTs, and fully used LUT flip-flop pairs are 65178, 40904, and 3655, respectively. The complexity of CryptoVVSHP is about 23% higher than VVSHP.