Design of a 3-channel 5 Gb/s/ch deserializer array for high-speed parallel links

A novel 3-channel 5 Gb/s/ch deserializer (DeSER) array is designed and fabricated in a standard 0.18 μm CMOS technology for applications for multi-channel 5 Gb/s/ch parallel links. The 3-channel array consists of one PLL-based DeSER and two DLL-based DeSERs. With a half-rate version of PLL and DLL, the corresponding PFD and PD are improved to realize the function of a 1:2 DeSER implicitly, respectively. The PLL and DLL techniques are combined to deal with the clocking-related issues for the DeSER array, which can come to a good tradeoff between compactness, low power dissipation, reliability, etc. Measured results demonstrate that the DeSER array works properly with no need of reference clock, off-chip tuning, external components, and any specified inter-channel skew. It achieves a power consumption of 380 mW from a single supply of 1.8 V, and a die area of 1,200 μm × 943 μm (including pads) with an average channel width of 250 μm/ch.