Ultra-low power subthreshold current-mode logic utilising PMOS load device

Ultra-low power subthreshold current-mode logic utilising PMOS load device

A novel approach for implementing MOS current-mode logic circuits that can operate with ultra-low bias currents is introduced. The measurements of test structures fabricated in 0.18 μm CMOS technology show that the proposed PMOS load device concept can be utilised successfully for bias currents as l...

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Veröffentlicht in:Electronics letters 2007-08, Vol.43 (17), p.1-1
Hauptverfasser: Tajalli, A, Vittoz, E, Leblebici, Y, Brauer, E J
Format: Artikel
Sprache:eng
Schlagworte:
Bias
CMOS
Devices
Frequency ranges
High gain
Logic
Logic circuits
Metal oxide semiconductors
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Zusammenfassung:A novel approach for implementing MOS current-mode logic circuits that can operate with ultra-low bias currents is introduced. The measurements of test structures fabricated in 0.18 μm CMOS technology show that the proposed PMOS load device concept can be utilised successfully for bias currents as low as 1 nA, achieving sufficiently high gain over a wide frequency range.
ISSN:0013-5194
1350-911X