Memory-controlled frequency divider for fractional-N synthesisers

Memory-controlled frequency divider for fractional-N synthesisers

A new programmable frequency divider technique based on the memory-control of a prescaler is presented. It is particularly suited to FPGA or PLD implementations and for use in conjunction with stored-sequence or other fractional-N frequency synthesiser architectures.

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Bibliographische Detailangaben
Veröffentlicht in:Electronics letters 2006-10, Vol.42 (21), p.1-1
Hauptverfasser: Brennan, P V, Jiang, D, Wang, H
Format: Artikel
Sprache:eng
Schlagworte:
Field programmable gate arrays
Frequency dividers
Prescalers
Synthesisers
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Zusammenfassung:A new programmable frequency divider technique based on the memory-control of a prescaler is presented. It is particularly suited to FPGA or PLD implementations and for use in conjunction with stored-sequence or other fractional-N frequency synthesiser architectures.
ISSN:0013-5194
1350-911X