A Review of Noise Susceptible Transistor in Dynamic Logic Circuits

Noise is becoming a major concern in digital systems due to the insistent scaling development in devices and interconnections. In this paper disputes related to process variations, timing, noise suppression, and power are investigated here for performance optimization. A weak PMOS keeper logic is used to improve the scaling of dynamic gates. The keeper has an overhead of one field-effect transistor per gate plus a portion of a shared current mirror. This keeper circuit technique is proposed in this paper for simultaneous power reduction and speed enhancement of domino integrated circuits. The threshold voltage of the keeper logic is modified during circuit operation to decrease the contention current without giving up noise immunity. The charge sharing can also be eliminated by pre-charging internal node.