Characterization of SiO sub(2)/SiC Interfaces Annealed in N sub(2)O or POCl sub(3)

This paper reports a comparative characterization of SiO sub(2)/SiC interfaces subjected to post-oxide-deposition annealing in N sub(2)O or POCl sub(3). Annealing process of the gate oxide in POCl sub(3) allowed to achieve a notable increase of the MOSFET channel mobility (up to 108 cm super(2)V super(-1)s super(-1)) with respect to the N sub(2)O annealing (about 20 cm super(2)V super(-1)s super(-1)), accompanied by a different temperature behaviour of the electrical parameters in the two cases. Structural and compositional analyses revealed a different surface morphology of the oxide treated in POCl sub(3), as a consequence of the strong incorporation of phosphorous inside the SiO sub(2) matrix during annealing. This latter explained the instability of the electrical behaviour of MOS capacitors annealed in POCl sub(3).