Low-power low-area network-on-chip architecture using adaptive electronic link buffers

In the deep sub-micron regime, the performance of network-on-chip (NoC) architectures, is bound by the limited power and area budget. Proposed is a low-power low-area NoC architecture using a novel power-efficient control circuit that enables repeaters along the interrouter links to function as adap...

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Veröffentlicht in:	Electronics letters 2008-04, Vol.44 (8), p.1-1
Hauptverfasser:	Sarathy, A, Kodi, A K, Louri, A
Format:	Artikel
Sprache:	eng
Schlagworte:	Adaptive control systems Architecture (computers) Buffers Circuits Electronics Links Routers Simulation
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