Delay-locked loop technique for temperature stabilisation of internal delays of CMOS FPGA devices

A delay-locked loop (DLL) technique for use with typical CMOS field programmable gate array (FPGA) devices is presented. It allows for temperature stabilisation of the internal delays of the devices, especially when the digital delay lines are designed. The voltage V^sub cc^ supplying the FPGA device is varied within a limited range by the DLL, to stabilise the internal delays of the device under changes in the ambient temperature. The method is illustrated, by presenting results of the realisation of an interpolating time counter with 200ps resolution, implemented on a single CMOS FPGA device.