Design and Modeling of Schmitt Trigger-based Sub-Threshold 8T SRAM for Low Power Applications

This paper presents the design of Schmitt trigger-based 8T SRAM Architecture for low power sub-threshold (or) near-threshold CMOS SRAM for power constrained Applications. Power Consumption, Power Dissipation and Leakage Power are the main factors in the IC Design. Memory unit is the primary block in design of any chip like Micro Processor and Micro Controller. As SRAMs comprise a significant percentage of the area and power for many digital chips and leakage can dominate total chip leakage. The proposed paper used to reduce the leakage power by using High-Vth nMOS as pull-down transistors for standard 6T SRAM. This paper demonstrates the Architecture Design and Analysis of 256bitcell 8T SRAM in 45nm technology. The design implementation and analysis is performed using 45nm CMOS technology in CADENCE IDE.