LEAKAGE POWER REDUCTION OF ON CHIP SRAM CELLS

The exponential growth of battery based portable applications mandatory new SRAM cell but this cell stand by leakage power has become a major issue in recent trend low power fabrication with technology scaling and for high temperature operations. This paper has emphasized on low power dissipation, read/write delay and stability of SRAM cell. The paper shows the performance of a new LP12T cell. The proposed LP12T cell is compared with traditional LP10T and 6T cell on MICROWIND 3.1 simulator using BSIM4 model for 120 nm and 65 nm at wide range of temperature. The average power dissipation is reduced for 120 nm and 65 nm, respectively, and the time response for read/write operation is slightly improved compared to LP 10T and 6T cell at mentioned scale.