Techniques for Sub-threshold Leakage Reduction in Low Power CMOS Circuit Designs

Power dissipation is a key consideration in the design of nano-scale CMOS VLSI circuits. Various techniques have been proposed for reduction of leakage in CMOS transistors. As the technology is emerging power dissipation due to leakage current has become a major contributor of total power consumption in the integrated devices. For high performance and device reliability, reduction of power consumption is highly desirable. Thus the importance of low power circuits has increased currently. The trend of scaling down has led to the increase in sub threshold leakage current and hence static power consumption. In this paper the different leakage reduction techniques for deep submicron technologies are focused comprehensively. The predominating sub threshold leakage current problem can be overcome by techniques like stacking of transistors, power gating, optimal body bias voltage generation at the circuit level thus providing a large range of choices for low-leakage power VLSI designers.