Modeling of Physical Defects in PN Junction Based Graphene Devices

Graphene’s exceptional electro-mechanical properties make it a strong contender to replace silicon-based Complementary Metal-Oxide Semiconductor (CMOS) devices in the future. Among other novel material-based devices, graphene is pushing the research community to find new technological solutions that exploit its special characteristics. As it is a semimetal, the key challenge for graphene-based devices to be used in digital circuits is introducing band gap. Among the proposed approaches, electrostatic doping represents a key option. It allows the implementation of graphene pn junctions through which building a new class of reconfigurable logic gates is possible. This devices are analyzed in this work. Recent works presented a quantitative analysis of such gates in terms of area, delay and power consumptions, confirming their superiority w.r.t. CMOS technologies below the 22 nm. This paper explores another dimension, that is testability, and proposes a study of possible physical defects that might alter the functionality of the graphene logic gates. Two major kinds of manufacturing defects, which are possible in these gates, namely the S h o r t s between the device’s terminals and O p e n terminals, are considered. These faults have been injected into non faulty devices at the SPICE-level and the resulting behavior is mapped to appropriate fault model. Most of such models belong to the CMOS domain, but for some specific class of defects, new fault definitions are needed.