Extrinsic and Intrinsic Charge Trapping at the Graphene/Ferroelectric Interface

The interface between graphene and the ferroelectric superlattice PbTiO3/SrTiO3 (PTO/STO) is studied. Tuning the transition temperature through the PTO/STO volume fraction minimizes the adorbates at the graphene/ferroelectric interface, allowing robust ferroelectric hysteresis to be demonstrated. “Intrinsic” charge traps from the ferroelectric surface defects can adversely affect the graphene channel hysteresis and can be controlled by careful sample processing, enabling systematic study of the charge trapping mechanism.