Data-Parallelism Based Hardware Architecture for the Intra-Coding Module Used in the H.264/AVC Encoder

In this paper, we propose a hardware architecture for the intra-coding module used in the H.264 encoder. The proposed architecture is based on data-parallelism principles, with a 128-bit data input. This data input is retrieved from a DDR2 memory using an intelligent memory controller specially designed for the H.264 encoder. Unlike other architectures using different intra-prediction modes in parallel, we propose to implement the different modes in series to avoid an excessive use of FPGA resources. This also provides the ability to process data in parallel. In this manner, we can ensure a pipelined architecture to reduce the required number of clock cycles to process each macroblock. Data-Parallelism based hardware architectures are proposed for the intra-prediction, the integer transform, the quantization, the inverse integer transform, the inverse quantization, and the mode decision modules. Results and performance measurements of the intra-coding module were validated on the Xilinx Virtex5-ML501 platform. The proposed architecture occupies 18 % of the FPGA’s resources and operates at a maximum frequency of 155MHz.