Optimal design for a high performance H-JLTFET using HfO sub(2) as a gate dielectric for ultra low power applications

In this paper we have proposed an optimal design for a hetero-junctionless tunnel field effect transistor (TFET) using HfO sub(2) as a gate dielectric. The device principle and performance are investigated using a 2D simulator. During this work, we investigated the transfer characteristics, output characteristics, transconductance, G sub(m), output conductance, G sub(D), and C-Vcharacteristics of our proposed device. Numerical simulations resulted in outstanding performance of the H-JLTFET resulting in I sub(ON) of similar to 0.23 mA mu m super(-1), I sub(OFF) of similar to 2.2 10 super(-17) A mu m super(-1), I sub(ON)/I sub(OFF) of similar to 10 super(13), sub-threshold slope (SS) of similar to 12 mV dec super(-1), DIBL of similar to 93 mV V super(-1) and V sub(th) of [sime]0.11 V at room temperature and V sub(DD) of 0.7 V. This indicates that the H-JLTFET can play an important role in the further development of low power switching applications.