A Time-Domain Architecture and Design Method of High Speed A-to-D Converters with Standard Cells

A Time-Domain Architecture and Design Method of High Speed A-to-D Converters with Standard Cells

In this paper, we describe a new method to deal with analog signal in time domain. The method converts voltage signal to time-interleaved phase modulation signal of clock edge. After being amplified by a new time amplifier (TA), phases of the signal are converted to digital codes by successive appro...

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Veröffentlicht in:IEICE transactions on electronics 2013, Vol.E96.C (6), p.813-819
Hauptverfasser: Takayama, Masao, Dosho, Shiro, Takeda, Noriaki, Miyahara, Masaya, Matsuzawa, Akira
Format: Artikel
Sprache:jpn
Schlagworte:
Approximation
Chips
Clocks
Converters
Electric potential
High speed
Mathematical analysis
Voltage
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Beschreibung
Zusammenfassung:In this paper, we describe a new method to deal with analog signal in time domain. The method converts voltage signal to time-interleaved phase modulation signal of clock edge. After being amplified by a new time amplifier (TA), phases of the signal are converted to digital codes by successive approximation time-to-digital converter (SA-TDC). The test chip includes 8 interleaved 4bit SA-TDCs with short latency. The chip operates up to 4.4GHz. The measured ENOB is 3.51bit and FOM is 0.49pJ/conv.
ISSN:0916-8524
1745-1353
DOI:10.1587/transele.E96.C.813