Output capacitance on GaN HEMTs in correlation to its transistor geometry and sheet resistance

Output capacitance (Cout) measurements on AlGaN‐GaN HEMTs with different field plate (FP) sizes and different EPI configurations as well as different sheet resistances owing to surface preparation have been performed at VDS = 10 and 40 V. A model is proposed where Cout is composed by a horizontal intrinsic part C1 and a vertical FP part C2. It could be shown that in case of large FPs and at high voltage measurements Cout via C2 is very sensitive to the vertical layer‐sequence including surface preparation. Simulations performed on the same transistor structures and at same meas‐ urement conditions confirm well the measured values by assumption of surface traps in the 1012 cm‐2‐range. Additionally, it could be demonstrated that the output RF‐power of the transistors with FP and at high voltage is directly correlated to Cout on transistors with high SD‐voltage. It is proposed that by such Cout‐measurements important information can be deduced about the vertical layer configuration including surface states and the transistor performance, e.g. regarding output power. (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)