A Stoppable clock based Approach for Low Power Network Interface Design in a Network on Chip

A low-power design is an essential and important issue for portable or mobile systems. Network on chip (NoC) will become the main communication platform for this kind of Systems. To address the problem of an energy efficient design of NoC, we must decrease the power consumption of NoC components. To reduce NoC consumption, we must reduce the power of NoC components such as Network Interface (NI) components. The architecture of NIs component must be modular to allow intellectual propriety (IP) module and interconnections to be designed independently from each other and its power must be kept as low as possible. In this paper, we present new modular NI architectures between IPs and router with low power constraints. The modular design is obtained through two separations between data flows and IP side and the network side. The low power is obtained by the implementation of a mechanism based on stoppable clock technique for power saving. The stoppable clock technique allows us to shut down each sub module when it is not running. Experimental results show that the Modularity and the stoppable clock technique aspects integrated in the proposed NI allow a significant reduction in terms of power between stoppable and baseline architectures while increasing at same time the area and decreasing the speed of NIs.