RTN assessment of traps in polysilicon cylindrical vertical FETs for NVM application

•Random telegraph noise and low-frequency noise in polysilicon device.•The impact of electron trapping and detrapping events in scaled non-volatile memories.•Behavior of gate oxide, interface and polysilicon traps in n-type polysilicon cylindrical vertical transistors. In this work the drain current random telegraph noise (RTN) in polysilicon-channel cylindrical vertical FET structures is studied experimentally. We show that single electron trapping events can induce significant drain current fluctuations during read operation in deeply scaled non-volatile memories (NVMs). Low-frequency (LF) noise and capture and emission time constants of the traps are also analyzed at different gate and drain bias conditions. Two independent types of traps are identified in this study, which we categorize as slow and fast states. In this paper, we show that the RTN most likely originates from traps in the highly defective channel region, in addition to the fluctuations caused by defects in the oxide close to the interface with the channel.