A low-power oriented architecture for H.264 variable block size motion estimation based on a resource sharing scheme

In the Advanced Video Coding (AVC) standard, motion estimation (ME) adopts many new features to increase the coding performances such as block matching algorithm (BMA), motion vector prediction (MVP) and variable block size motion estimation (VBSME). However, VBSME is utilized in the MPEG4-AVC/H.264 standard which leads to high computational complexity and data dependency that make the hardware implementation very complex. This paper proposes a flexible VLSI architecture for full-search VBSME (FSVBSME), allowing the partitioning of the source frames into sixteen 4×4 sub-blocks and using a MVP scheme. A clock gating technique based on a distributed control unit is used for power saving. The proposed architecture was designed by Synopsys Design Compiler with 0.13μm CMOS standard cell library. Under a clock frequency of 500MHz, it allows a power consumption of about 131mW. Our VLSI architecture, compared with contemporary ones, can offer higher processing speed, lower power consumption, lower latency and lower gate count complexity. ► This paper presents an architecture for FSVBSME and its VLSI implementation. ► The proposed architecture can achieve 41 motion vectors of a MB. ► This architecture promotes reuse of the previous calculated SAD. ► Power consumption is reduced.