A 2.488a11.2 Gb/s SerDes in 40 nm low-leakage CMOS with multi-protocol compatibility for FPGA applications

This paper presents the design and Silicon verification of a 2.488a11.2 Gbps multi-standard SerDes transceiver in a 40 nm low-leakage CMOS process. The paper explores the architectural and circuit techniques used to meet the stringent requirements of the high-speed SerDes and to mitigate the perform...

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Veröffentlicht in:Analog integrated circuits and signal processing 2014-02, Vol.78 (2), p.259-273
Hauptverfasser: Vamvakos, Socrates, Gauthier, Claude, Rao, Chethan, Wang, Alvin, Canagasaby, Karthisha, Abugharbieh, Khaldoon, Choudhary, Prashant, Dabral, Sanjay, Desai, Shaishav, Hassan, Mahmudul, Hsieh, K, Kleveland, Bendik, Mandal, Gurupada, Rouse, Richard, Saraf, Ritesh, Yeung, Jason, Cao, Ying
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Sprache:eng
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Zusammenfassung:This paper presents the design and Silicon verification of a 2.488a11.2 Gbps multi-standard SerDes transceiver in a 40 nm low-leakage CMOS process. The paper explores the architectural and circuit techniques used to meet the stringent requirements of the high-speed SerDes and to mitigate the performance impact of the low-leakage process. A system modeling approach is described, which is used for optimizing the architectural trade-offs. The transceiver makes use of a low-jitter LC phase locked loop to enable high-reliability system design. The design has 420 fs RJrms and consumes 30.1 mW/Gbps at 11.2 Gbps.
ISSN:0925-1030
1573-1979
DOI:10.1007/s10470-013-0172-1